Through Silicon Via Fabrication with Low-k Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

摘要

Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal-oxide-silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with Iow-k material with an effective dielectric constant of ~2.8. Low-k liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-k liner reduces the TSV capacitance by ~27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current-voltage (I-V) measurement is carried out to monitor and study the leakage of the Iow-k liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N_2/H_2) at 350 ℃ for 30min successfully reduces the leakage current density by ~1.6×, to a mid-distribution value of ~6.8 × 10~(-6)A/cm~2.