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首页> 外文期刊>IEEE Transactions on Reliability >A Study on Effects of Copper Wrap Specifications on Printed Circuit Board Reliability
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A Study on Effects of Copper Wrap Specifications on Printed Circuit Board Reliability

机译:铜套规格对印刷电路板可靠性的影响研究

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During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrapwas sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 mu m/0.197 mil for all via types). Experimental results corroborated bymodeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
机译:在制造用于飞行项目的印刷电路板(PCB)的过程中,发现一家欧洲制造商正在按照欧洲标准制造其板,该标准不需要在通孔上包铜。在包含目标板的面板上的样片上测得的铜包裹量少于IPC-6012 Rev B,Class 3中指定的量。为帮助确定板的可靠性和可用性,进行了三组测试和模拟运行。本文介绍了测试结果以及仿真和破坏性物理分析的结果。第一个实验涉及对欧洲制造商提供的面板中的试样进行热循环。在17000次循环之后,测试没有失败就被停止了。第二组加速测试涉及将由FR4和聚酰亚胺制成的测试样品与不同量的铜包裹物的热疲劳寿命进行比较。同样,测试没有发现任何故障。第三项测试涉及将互连应力测试样片与通孔和盲孔一起使用,这些试件经受高温以加速疲劳失效。正如预期的那样,虽然有故障,但故障是在桶裂处造成的。除了实验之外,本文还讨论了使用模拟软件进行有限元分析的结果,该软件用于通过稳态分析对热应力下的镀通孔进行建模,还显示出主要的失效模式是桶裂纹。测试表明,尽管人们希望将铜箔纸作为滚镀和铜箔层之间的对接接头的更好选择,但可制造性仍然具有挑战性,并且试图满足要求通常会导致降低板子可靠性的特征。本文讨论的实验和仿真工作表明,对铜绕线的标准要求不会影响整体电路板的可靠性,尽管应该补充一点,对接接头的设计比减少铜绕线的设计具有更高的风险。 。研究进一步表明,从3级到2级的包裹镀层厚度的采购要求对可靠性几乎没有影响(所有通孔类型最小5微米/0.197百万美元)。通过建模证实的实验结果表明,应力最大值在枪管内部,而不是在包裹位置。实际上,确定铜包膜的存在对可靠性没有明显影响。

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