Crosstalk Effects Caused by Single Event Hits in Deep Sub-Micron CMOS Technologies

摘要

In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of charge deposited to cause an upset increases, and as the interconnect length increases