6-bit CMOS Digital Attenuators With Low Phase Variations for -Band Phased-Array Systems

摘要

This paper presents 6-bit CMOS digital step attenuators with low phase variations. To mitigate the insertion phase variation of conventional switched Pi/T attenuators, the proposed attenuators employ a compensation circuit. This includes a low-pass filter for phase/amplitude correction. Analysis and comparison of two types of Pi-attenuators with the inductive and capacitive correction circuits are described. The two types of attenuators are fabricated using a 0.18-$mu{hbox{m}}$ CMOS process. The attenuators have a maximum attenuation range of 31.5 dB with 0.5-dB steps (64 states). The attenuators with the inductive and capacitive correction structures, respectively, exhibit root mean square (rms) amplitude errors of less than 0.3 and 0.4 dB, and rms phase errors of less than 3.5$^{circ}$ and 2$^{circ}$ at 8–12 GHz. The insertion losses are 8.7 and 10.5 dB at 10 GHz, respectively. The input 1-dB compression points are 15 and 13 dBm at 10 GHz, and the total chip sizes, excluding pads, are ${hbox{1.25}}times {hbox{0.4}}~{hbox{mm}}^{2}$ and ${hbox{0.67}}times {hbox{0.5}}~{hbox{mm}}^{2}$.