SET Response of the Selectively Implanted Deep N-Well —Comparison With Dual Well and Triple Well

摘要

The SET response of the selectively implanted deep N-well (SIDNW) was compared with dual well (DW) and triple well (TW) structures by way of heavy-ion experiments on a 65-nm bulk CMOS process. Experimental data produced by P-hit target chains with SIDNW show that a 34.2% decrease in the average pulse width and a 32.1% decrease in the SET cross section is achieved when compared with the DW process, demonstrating the effectiveness of SIDNW in mitigating PMOS SETs by reducing the parasitic bipolar effect during charge collection. Heavy-ion test results on inverter chains, in which the SETs are generated in both PMOS and NMOS, indicate that the SIDNW can mitigate PMOS SETs without bringing adverse effects to the NMOS SETs, when compared with the DW and TW processes.