IC Failure Analysis Due to Charged Board Events by Measurements and Modeling of Discharging Currents Through IC Pins

摘要

Commercial integrated circuits (ICs) were assembled on several practical printed circuit board (PCB) structures, and the discharging currents through individual pins of the IC induced by charged board events (CBE) were measured using shielded Rogowski coils. The overall CBE measurement setup was modeled and validated using circuit simulations. The structures of PCBs and a test ground plane were effectively modeled using a multilayered finite-difference method. Electrostatic discharge protection circuits in the IC were also modeled as behavioral circuit models. From the measurement and modeling of the CBE discharging currents at the IC pins, IC failure mechanisms were analyzed according to PCB structure, decoupling capacitor, and discharging points. Several strategies for IC protection against CBE risks were also obtained.