Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction

摘要

A new low-complexity method to decode single symbol correction Reed-Solomon codes is proposed in this paper. This decoding algorithm takes advantage of the equivalent parity-check matrix representation to apply majority logic techniques that avoid the needs of computing Galois Field inversions, divisions and logarithms, unlike previous efficient solutions. The derived architectures allow to increase the order of the Galois Field, keeping similar area and delay results for the same message length. Hence, it is possible to configure the burst error capacity without compromising the decoder performance. Finally, due to the three-step procedure of the decoder: syndrome, magnitude estimation and majority logic, the decoding latency is reduced to two clock cycles without compromising the critical path improving latency between two and five times. The proposed decoder can obtain an area reduction of at least 44% for codes with high Galois Field order, i.e., GF(2(8)). The high level of customization in terms of data word length and the high frequency and low area make these decoders suitable for a wide range of storage systems.