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Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography

机译:双模式平版印刷中双峰CD分布的时序收益率颜色重新分配和详细放置扰动

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摘要

Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of “bimodal” challenges for timing analysis and optimization. We assess the potential impact of bimodal CD distribution on timing analysis and guardbanding, and find that the traditional “unimodal” characterization and analysis framework may not be viable for DPL. We propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an integer linear programming-based maximization of “alternate” mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure “double patterning correctness” after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable engineering change order (ECO) impact. With a 45 nm library and open-source design testcases, our timing-aware recoloring and placement optimization together achieve up to 271 ps (respectively, 55.75 ns) reduction in worst (respectively, total) negative slack, and 70% (respectively, 72%) reduction in worst (respectively, total) negative slack variation, respectively.
机译:对于存储器产品,目前正在生产双图案光刻(DPL),并且广泛认为32纳米节点上的逻辑产品是不可避免的。 DPL会在两次曝光中分解并打印关键层布局的形状。在传统的单次曝光光刻中,相邻的相同布局特征将具有相同的平均临界尺寸(CD)和与空间相关的CD变化。但是,使用DPL,相邻要素可能具有截然不同的平均CD和不相关的CD变化。这为时序分析和优化引入了一系列新的“双峰”挑战。我们评估了双峰CD分发对时序分析和保护带的潜在影响,并发现传统的“单峰”表征和分析框架可能不适用于DPL。我们提出了新的双峰感知时序分析和优化方法,以提高使用DPL制造的基于标准单元的设计的时序产量。我们的第一个贡献是基于对单元布局的详细分析,采用DPL感知的时序建模方法。我们的第二个贡献是在时序关键路径中实例的“替代”蒙版着色基于整数线性规划的最大化,以最大程度地减少有害协方差和性能变化。第三,我们提出了一种基于动态编程的详细布局算法,该算法可解决蒙版着色冲突,可用于确保布局后甚至是详细布线后的“双图案正确性”,同时以可管理的工程变更单将时序关键型单元的位移降至最低(ECO)影响。借助45 nm库和开源设计测试案例,我们的可感知时序的重新着色和布局优化共同实现了271 ps(分别为55.75 ns)的最差(分别为总)负松弛减少和70%(分别为72)的减少。 %)分别减少了最差的(分别是总的)负松弛变化。

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