Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

摘要

This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on-capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multi-million-gate scan designs. In case the scan design contains multiple synchronous clock domains, each group of synchronous clock domains is treated as a clock group and tested using a launch aligned or a capture aligned LOC scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately $1.7X$ to $2.1X$, while the ATPG runtime was increased by 10% to 50%, when compared to the one-hot clocking scheme alone.