Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware

摘要

We revisit the specification of control circuits and protocols written as regular expressions, and propose a synthesizable subset of the sequences that can be written in the property specification language and system Verilog assertions standards. We give a formal semantics of the sequence operators that can directly be interpreted in terms of circuits, and provide a modular method to achieve the automatic generation of compliant hardware from specifications written as temporal sequences. The method also generates assertions to check the completeness and consistency of the specifications. Results obtained on classical benchmarks show the efficiency of our technique. Finally, we discuss the applications of our prototype tool in an assertion-based verification flow.