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首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II
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Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II

机译:集成电路ESD稳健性的可扩展和多功能设计指导工具 - 第二部分

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This article gives a detailed insight on a machine learning procedure to infer quasistatic quantities of electrostatic discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of transmission line pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article.
机译:本文对机器学习程序提供了详细的洞察,以从网列表中从它们的实例参数推断静电放电量(ESD)保护结构的Quasistatic量。它令人途中的传输线脉冲数据集(TLP)I-V曲线已经从许多瞬态电气仿真获得。通过嵌套的交叉验证来执行机器学习算法的调整和它们广泛的预测性能的量化。由此产生的拟合分析模型包含在称为ESD IP Explorer的工具中,负责提供系统和可扩展的ESD验证方法。已经专门实施以覆盖整个设计流程并符合自定义电路架构的该工具在前面的文章中描述。

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