Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the [2/sup n/-1, 2/sup n/, 2/sup n/+1] modula set

摘要

This work presents a high speed realization of a residue to binary converter for the (2/sup n/-1, 2/sup n/, 2/sup n/+1), moduli set, which improves upon the best known implementation by almost twice in terms of overall conversion delay. This significant speedup is achieved by using just three extra two input logic gates. Interestingly, by exploiting certain symmetry in operands, we also reduce the hardware requirement of the best known implementation by n-1 full adders. Finally, the proposed converter eliminates the redundant representation of zero using no extra logic.