A New Technique for On-Chip Error Estimation and Reconfiguration of Current-Steering Digital-to-Analog Converters

摘要

In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-μm CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.