Background Interstage Gain Calibration Technique for Pipelined ADCs

摘要

A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic analog-to-digital converters (ADCs). Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital post-processing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described by Murmann and Boser. Simulation results are presented for a 12-bit pipelined ADC architecture, similar to that described by Murmann and Boser, using nonideal interstage residue amplifiers. With calibration, the simulations show a signal-to-noise-and-distortion-ratio performance of 72 dB and a spurious-free dynamic range performance of 112 dB, with calibration tracking time constants of approximately 8 × 10{sup}5 sample periods, which is over ten times faster than that reported by Murmann and Boser at a similar performance level.