Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW Sensors—II: Theory

摘要

Synthesizers for the generation of frequency- or phase-modulated signals are required in communications, sensing, and many other fields and applications. The widespread use of phase-locked loops (PLLs) as major building blocks in current systems requires accurate models and methods for eliminating the influence of statistical and deterministic errors in the synthesized signals. We propose a novel iterative phase-error-measurement and -compensation procedure applicable in PLL-based synthesizers, for which the mathematical background is presented, and a detailed algorithmic description is given in this work. From a mathematical PLL system model and its response to a periodic excitation by the modulating signal, a method for measuring the instantaneous output signal phase and the actual transfer function of the PLL is derived. It is shown how this knowledge can advantageously be used for pre-distorting the synthesizer input signal to eliminate deterministic errors and to obtain an accurate output phase curve.