首页> 外文期刊>IEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing >Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process
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Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process

机译:用于深亚微米CMOS工艺中RF频率合成的基于数字振荡器(DCO)的架构

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A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed △∑ dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency syn-thesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-μm CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is -112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below -62 dBc, while the far-out spurs are below -80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.
机译:提出并演示了一种新颖的基于数字控制振荡器(DCO)的架构,用于无线RF应用中的频率合成。故意避免使用模拟调谐电压控制线。通过高速△∑抖动可以实现精细的频率分辨率。模拟电路的其他缺陷可通过数字方式进行补偿。提出的想法可以使用复杂的信号处理算法来采用全数字频率合成器,这些算法是在最先进的深亚微米数字CMOS工艺中实现的,几乎不允许模拟扩展。它们还促进了与数字后端在单个硅芯片上的经济高效集成。演示器测试芯片与DSP一起采用数字0.13μmCMOS工艺制造,该DSP用作具有大量数字门的数字基带处理器,以研究噪声耦合。在500kHz偏移处的相位噪声为-112 dBc / Hz。近端杂散音低于-62 dBc,而远端杂散低于-80 dBc。提出的想法已被并入商业蓝牙收发器中。

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