Bit-Error-Rate Estimation for High-Speed Serial Links

摘要

High-performance serial communication systems often require the bit error rate (BER) to be at the level of 10-12 or lower. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems. In this paper, we show that the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit can be used to estimate the BER effectively without comparing each captured bit for error detection. This analysis is also useful for designing a CDR circuit for systems whose jitter spectral information is known. Experimental results comparing the estimated and measured BER on a 2.5-Gb/s commercial CDR circuit demonstrate the high accuracy of the proposed technique