首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes
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Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes

机译:低密度奇偶校验卷积码的终止序列生成电路

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Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we present a construction method for termination sequence generation circuits suitable for field-programmable gate arrays and application-specific integrated circuits. This method uses linear algebra to determine the termination sequence for a small number of states of the encoder and converts these solutions into a sequential circuit. Results are presented for several realizations of termination circuits for a (128,3,6) LDPC-CC
机译:低密度奇偶校验卷积码(LDPC-CC)是其流行的面向块编码的补充,并且可能更适合某些通信应用。这些包括流语音,视频和分组交换网络。为了有效地使用这些代码,我们必须生成类似于常规卷积代码中使用的终止序列。在本文中,我们提出了一种适用于现场可编程门阵列和专用集成电路的终止序列生成电路的构造方法。该方法使用线性代数确定编码器少数状态的终止顺序,并将这些解转换为顺序电路。给出了(128,3,6)LDPC-CC端接电路几种实现的结果

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