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A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors

机译:使用单电子器件和CMOS晶体管的新型混合锁相环频率合成器

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This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.
机译:本文提出了一种使用单电子器件(SED)和金属氧化物半导体(MOS)场效应晶体管的新型锁相环(PLL)频率合成器。 PLL频率合成器主要由单电子晶体管(SET)/ MOS混合压控振荡器电路,单电子(SE)旋转栅/ MOS混合相频检测器(PFD)电路和SE旋转栅/ MOS混合电路组成分频器。通过操纵单个电子可以实现相频检测和分频功能。我们提出了一个SPICE模型来描述基于MOSFET的SE旋转栅的行为。作者模拟了PLL模块电路和整个PLL合成器的性能。仿真结果表明,该电路在室温下可以很好地执行PLL频率合成器的工作。 PLL合成器非常紧凑。晶体管的总数小于50。建议的PLL电路的功耗小于3 uW。作者讨论了制造公差,背景电荷和SE传输精度对PLL电路性能的影响。提出了一种补偿SEDs参数离散度的技术。

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