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A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers

机译:固定宽度展位乘法器的高精度自适应条件概率估计器

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In this paper, a single compensation formula of adaptive conditional-probability estimator (ACPE) applied to fixed-width Booth multiplier is proposed. Based on the conditional-probability theory, the ACPE can be easily applied to large length Booth multipliers (such as 32-bit or larger) for achieving a higher accuracy performance. To consider the trade-off between accuracy and area cost, the ACPE provides varying column information $w$ to adjust the accuracy with respect to system requirements. The 16-bit ACPE Booth multiplier with $w=3$ reduces 28.9% silicon area with only 0.39 dB signal-to-noise ratio (SNR) loss when compared with post-truncated (P-T) Booth multiplier. Furthermore, the ACPE Booth multipliers are applied to two-dimensional (2-D) discrete cosine transform (DCT) to evaluate the system performance. Implemented in a TSMC 0.18 $mu hbox{m}$ CMOS process, the DCT core with ACPE $(w=3)$ can save 14.3% area cost with only 0.48 dB peak-signal-to-noise-ratio (PSNR) penalty compared to P-T method.
机译:提出了一种应用于固定宽度布斯乘数的自适应条件概率估计器(ACPE)的补偿公式。根据条件概率理论,可以将ACPE轻松应用于大长度的Booth乘法器(例如32位或更大),以实现更高的精度性能。为了考虑精度和面积成本之间的折衷,ACPE提供了不同的列信息$ w $来根据系统要求调整精度。与后截断(P-T)展位乘法器相比,$ w = 3 $的16位ACPE展位乘法器可减少28.9%的硅面积,并且仅损失0.39 dB的信噪比(SNR)。此外,ACPE展位乘法器还应用于二维(2-D)离散余弦变换(DCT),以评估系统性能。采用TSMC 0.18 $ mu hbox {m} $ CMOS工艺实现,具有ACPE $(w = 3)$的DCT内核可节省14.3%的面积成本,而峰峰值信噪比(PSNR)仅为0.48 dB与PT方法相比。

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