Design of $2 times {rm V}_{rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 times {rm V}_{rm DD}$ Thin-Oxide Devices

摘要

A new $2times {rm V}_{rm DD}$-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only $1 {rm xV}_{rm DD}$ devices can successfully transmit and receive $2times {rm V}_{rm DD}$ signal. Utilizing this technique with only $1 {rm xV}_{rm DD}$ devices, the digital logic gates are also modified to have $2 {rm xV}_{rm DD}$-tolerant capability. With $2 {rm xV}_{rm DD}$ -tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from $2times {rm V}_{rm DD}$ signal and provide compensation control to the $2times {rm V}_{rm DD}$-tolerant I/O buffer without suffering the gate-oxide overstress issue.