Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

摘要

Switching speed, active power consumption, standby leakage current, and silicon area are major concerns in buffer design. A new Skewed-IO cell with two split inputs and two split outputs is proposed for low-leakage and high-speed buffer design in this paper. The triple-threshold-voltage buffers with the new Skewed-IO cells offer up to 68.3% and 13.2% reduction in standby leakage currents and propagation delay, respectively, as compared to the conventional static CMOS inverter based buffers under identical load capacitance conditions in a TSMC 65 nm CMOS technology.