A 0.8–4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking

摘要

The RF section of a software-defined-radio receiver front-end with harmonic rejection is presented. The proposed mixer-based receiver provides two programmable notches that can be located in any desired frequencies, e.g., the third and fifth harmonics of the sampling frequency in the proposed receiver. These rejections at the third and fifth harmonics are implemented using two RF-signal paths with a non-overlapped clocking strategy. The receiver also shows a good rejection at the seventh harmonic. The circuit is implemented in 130-nm CMOS and operates from a 1.5-V supply. Measurement results show that, for a 1-GHz RF input, the receiver has a harmonic rejection of 45 and 46 dB for the third and fifth harmonics, respectively. Moreover, the rejection of the seventh harmonic is as high as 44 dB for a 0.8-GHz RF input. Verifying the results on four different chips shows less than 2-dB variation in the rejection values. The receiver shows a noise figure of 3.8 dB at a baseband frequency of 5 MHz for a 1-GHz RF signal, with a power consumption of 33 mW.