A Configurable Noise-Shaping Band-Pass SAR ADC With Two-Stage Clock-Controlled Amplifier

摘要

This article presents an $8imes $ -oversampling successive approximation register (SAR) analog-to-digital converter (ADC) with configurable center frequency of noise shaping (NS), which permits the signal passband being configured to any one of the 8 equally divided sub-bands in the first Nyquist band. The configurable noise shaping is realized by an error-feedback (EF) structure with an adjustable 2-tap switched-capacitor (SC) FIR filter. Taking advantage of the sub-bands’ symmetry, the selection of the 8 sub-bands are determined by only a 2-bit controlled variable capacitor in the FIR filter in addition to one bit indicating which half-band the target sub-band is in. As a result, the configuration circuit is area efficient and introduces very little parasitic into the critical EF path. A 2-stage clock-controlled amplifier (CAMP) is proposed for the EF path, which can ensure gain and speed simultaneously through allocating reasonable currents into the gain stage and the driving stage separately. Implemented in 65-nm CMOS process, measurement results under a sampling rate of 10 MSPS show that the prototype achieves signal-to-noise-and-distortion (SNDR) of 71.9~74.6 dB in the 8 sub-bands with 625-KHz bandwidth, corresponding to a Scherier FoM of 171.4 -174 dB. The ADC prototype occupies 0.03-mm^{2 core area and consumes 70- $mu ext{W}$ average power at 1-V supply voltage.}