A 10.7b 300MS/s Two-Step Digital-Slope ADC in 65nm CMOS

摘要

This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify the operation polarity of the two-step digital-slope conversion. Besides, the two-step digital-slope conversion shares the unary DAC with different weights, which not only mitigates the resolution issues of the digital-slope quantizer but also converts the residue without requiring gain-error calibration. The two-step digital-slope ADC can be divided into three conversion steps and provide 1-bit, 5.7-bit, and 4-bit resolution for each conversion cycle. The digital-offset correction then encodes the three sets of outputs and subtracts the digital-offset caused by the feedback-process latency of the quantizers. The proposed two-step digital-slope ADC is manufactured using 1P9M 65-nm CMOS technology, and the active area of the prototype is 0.0946 square millimeter. At the Nyquist frequency, the SNDR and SFDR measured at 1.2 V, and 300 MS/s are 60.72 dB and 70.05 dB, respectively. With the power consumption of 6.2mW, the corresponding Walden FoM is 23.3 fJ/conversion-step.