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Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter

机译:基于自适应滤波器的去噪的自动化地震事件检测框架

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Automated detection of the P-wave arrival for real-time earthquake-early-warning-system employing conventional short-time-average/long-time-average (STA/LTA) algorithm is prone to suffer from erroneous detection due to high background noise. This paper introduces an enhanced variable step- size least mean square (EVSSLMS) algorithm for considerably improving the P-wave detection. The proposed event detection scheme employs the EVSSLMS algorithm for de-noising the seismic data followed by conventional STA/LTA algorithm to detect arrival of the P-wave. The EVSSLMS algorithm outperforms the existing trigonometric least mean square (TLMS), variable step-size LMS (VSSLMS), least mean logarithmic square (LMLS) and variable alpha-LMLS algorithms in terms of convergence speed and steady-state error and achieves a significant enhancement in detection accuracy by 42%, 33%, 25% and 23% at low signal-to-noise ratio (SNR) as compared to the existing TLMS, VSSLMS, LMLS, and variable-alpha LMLS algorithms, respectively. Moreover, a high-speed and low-complexity very-large-scale-integrated (VLSI) architecture has been implemented on both field-programmable-gate array (FPGA) and application-specific-integrated circuit (ASIC) platforms for realtime applications. Comparison of architectural performance of the proposed scheme with that of architecture designed to realize variable-alpha LMLS algorithm exhibits 36% less slice-delay-product whereas, its ASIC implementation exhibits 7.27% less areadelay-product, 9.31% less energy-per-sample with 5.2% more maximum achievable frequency.
机译:自动检测用于实时地震预警系统的P波到达,采用传统的短时平均/长时间平均(STA / LTA)算法易于由于高背景噪声而受到错误的检测。本文介绍了增强的可变梯度最小均方(EVSSLMS)算法,用于显着提高P波检测。所提出的事件检测方案采用EVSSLMS算法用于去噪,用于检测P波的传统STA / LTA算法的地震数据。 EVSLMS算法优于现有的三角度最小均方(TLMS),可变阶梯大小LMS(VSSLMS),最小均值对数方形(LMLS)和可变alpha-LMLS算法在收敛速度和稳态误差方面,实现了重要与现有TLMS,VSSLMS,LMLS和可变alpha LMLS算法相比,在低信噪比(SNR)上以42%,33%,25%和23%的检测精度增强。此外,在实地可编程门阵列(FPGA)和用于实时应用的特定于应用专用的集成电路(ASIC)平台上实现了高速和低复杂性非常大的集成(VLSI)架构。所提出的方案的架构性能比较旨在实现可变α1MLS算法的架构的架构表现表现出36%较少的切片延迟 - 产品,而其ASIC实施表现出7.27%较少的areadelay-产品,每种能量较低9.31%可实现5.2%的最大频率。

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