Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

Raviteja Theertham; Shanthi Pavan

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Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

机译：连续时间Delta-Sigma调制器中斩波伪像的统一分析，建模和仿真

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摘要

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT

机译：斩波是缓解连续时间delta-sigma调制器（CT）中闪烁噪声影响的有效方法

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《IEEE transactions on circuits and systems . I , Regular papers》 |2019年第8期|2831-2842|共12页
作者
Raviteja Theertham; Shanthi Pavan;
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Department of Electrical Engineering IIT Madras Chennai India;

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正文语种 eng
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关键词
Modulation; Analytical models; Bandwidth; Optical signal processing; Integrated circuit modeling; Transient analysis; Shape;

机译：调制;分析模型;带宽;光信号处理;集成电路建模;瞬态分析;形状;

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1. Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design [J] . Shanthi Pavan IEEE transactions on circuits and systems . I , Regular papers . 2017,第8期

机译：斩波积分器的分析及其在连续时间Δ-Σ调制器设计中的应用
2. A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC [J] . Jang MoonHyung, Lee Changuk, Chae Youngcheol IEEE Journal of Solid-State Circuits . 2021,第6期

机译：134-μW99.4-DB SNDR音频连续时间Δ-Σ调制器，具有切碎的负-R和三级FIR-DAC
3. Modeling Continuous-Time Delta-Sigma Modulator in MATLAB SIMULINK for System-Level Simulation and Specification Translation [J] . MATTHEW WEBB, HUA TANG WSEAS Transactions on Circuits and Systems . 2006,第12期

机译：在MATLAB SIMULINK中为系统级仿真和规范转换建模连续时间Delta-Sigma调制器
4. Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators [C] . Raviteja Theertham, Shanthi Pavan IEEE International Symposium on Circuits and Systems . 2020

机译：连续时间Delta-Sigma调制器中斩波伪像的统一分析，建模和仿真
5. Linearity Enhancement Techniques for High Performance Gm-C Based Continuous-Time Delta-Sigma Modulators [D] . Basak, Debajit. 2018

机译：基于高性能GM-C连续时间Δ-Σ调制器的线性增强技术
6. A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate [O] . Yao Xiao, Zhifei Lu, Zhaofeng Ren, 2020

机译：具有2.4Ghz时钟速率的100Mhz带宽80dB动态范围连续时间Δ-Σ调制器
7. Analysis and simulation of a cascaded delta delta-sigma modulator [O] . Joseph, D, Tarassenko, L, Collins, S 2001

机译：级联delta delta-sigma调制器的分析和仿真
8. 2-D Numerical Simulation and Analysis of a Simple Band Model for the Priz SpatialLight Modulator [R] . Barmore, G. D. 1996

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Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

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