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A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

机译:低密度奇偶校验码的概率并行翻转比特译码器

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This paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented inSection II. The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.
机译:本文提出了一种新的比特翻转(BF)解码器,称为概率并行BF(PPBF),用于二进制对称信道上的低密度奇偶校验码。在PPBF中,翻转操作以概率方式执行,这被证明可以显着提高纠错性能。 PPBF的优点还来自以下事实:在解码过程中不需要全局计算,并且所有计算都可以在本地计算单元中并行执行。与其他已知的BF解码器相比,PPBF极大地改善了工作频率和复杂性,同时在纠错方面获得了可观的收益。还介绍了PPBF的一种改进版本,称为非综合征PPBF,其中将全局综合征检查移出了关键路径,并提出了一种新的终止机制。为了显示新解码器在硬件效率和解码吞吐量方面的优越性,相应的硬件体系结构以 n 第二部分 n。专用集成电路的合成结果证实,与文献中的BF解码器相比,所提出的解码器的工作频率得到了显着提高,同时需要较低的复杂度才能有效地实现。

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