A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation

摘要

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of ≤ 0.1% - delay/1% - V{sub}(DD)- The design is fabricated in 0.25-μm CMOS technology and consumes 10 mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.