Self-Biased High-Bandwidth Low-Jitter l-to-4096 Multiplier Clock Generator PLL

摘要

A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13μm CMOS, the area is 0.182 mm{sup}2 and the supply is 1.5 V.