VLSI implementation of a maximum-likelihood decoder for the Golay (24, 12) code

摘要

J.H. Conway and N.J.A. Sloane (1986) have introduced an algorithm for the exact maximum-likelihood decoding of the Golay (24, 12) code in the additive white Gaussian noise channel that requires significantly fewer computations than previous algorithms. An efficient bit-serial VLSI implementation of this algorithm is described. The design consists of two chips developed using path-programmable logic (PPL) and an associated system of automated design tools for three- mu m NMOS technology. It is estimated that this decoder will produce an information bit every 1.6-2.4 mu s. Higher speeds can be achieved by using a faster technology or by replicating the chips to perform more operations in parallel.