With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in the satellite communication, wireless communication, and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this dissertation, a multi-rate LDPC decoder architecture is presented and implemented on a Xilinx field programmable gate array (FPGA) device. Using pin selection, three operating modes, namely, the irregular 1/2 code, the regular 5/8 code and the regular 7/8 code, are supported.; To suppress the error floor level, which is a common problem of LDPC code and limits its further adoption by many IEEE standards, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC-Orthogonal Frequency Division Multiplexing (OFDM) FPGA prototype system and achieves the superior measured performance of block error rate below 10-7 at SNR 1.8 dB.; To further exploit the challenges in the LDPC decoder VLSI implementation, the multi-rate decoder is implemented on silicon using TSMC 0.18um, 1.8V, 6-metal-layer process. The designed chip has a total area of 16mm2 and power dissipation estimation of 794mW at 100MHz working frequency. During the silicon implementation of the decoder, many challenges such as huge memory consumption, low test coverage, and complicated power-ground network design have been solved successfully. Consequently, the test coverage of the chip is as high as 96.2% and the maximum voltage drop is only 23mV.
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