An area-efficient parallel VLSI-architecture for the (24,12,8) Golay decoder with an optimized permutation decoding technique based on Wolfmann's algorithm is presented. The decoder uses a look-ahead error-correction structure and a carry-save computation to obtain the highspeed implementation. The hardware complexity was greatly reduced by using a high computation regularity which maps the cyclic syndrome calculation efficiently on a parallel architecture. It is shown that this new architecture for the Golay decoder can be easily implemented in CMOS technology to operate at a data rate above 1 Gbit/s.
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