Compact 32-bit CMOS adder in multiple-output DCVS logic for self-timed circuits

摘要

The paper presents a compact 32-bit carry look-ahead (CLA) adder in multiple-output differential-cascode voltage-switch (MODCVS) logic for delay-insensitive self-timed applications. This adder is structurally and functionally equivalent to a dynamic Manchester carry chain with an efficient organisation which exploits the advantages of MODCVS logic to reduce both the number of devices required and the routing area. The electrical simulation carried out on a standard CMOS 1.0μm design shows that this adder is similar in speed to the binary carry look-ahead adder previously reported, though it has a slightly higher average addition time. However, the MODCVS adder occupies 50/100 of the area, uses 36/100 fewer transistors and has 20/100 less dynamic power consumption. On comparing it with similar asynchronous adders, it minimises the worst-case delay, maintaining similar average delay, making it suitable in circuits with nonrandom input operands.