VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits

摘要

Self-timed adders are widely used since they compute in mean time. Traditionally, in order to achieve very high-speed performance they are realized using dynamic CMOS logic (Domino, DCVSL). However, recent works have demonstrated that efficient self-timed adders can also be realized using fully static CMOS circuits. In this paper, a new high-performance fully static 56-bit self-timed adder is presented. The proposed VLSI implementation uses overlapped execution circuits, which perform their computation by exploiting the initialization time elapsing between two consecutive operations. The new adder realized with AMS 0.6 /spl mu/m CMOS standard-cells shows an average addition time of /spl sim/3.3 ns, requires /spl sim/900000 /spl mu/m/sup 2/ of silicon area and consumes a maximum power of /spl sim/660 mW @300 MHz.