Hot-hole-induced degradation in polycrystalline silicon thin-film transistors: experimental and theoretical analysis

摘要

The application of bias stress with high source-drain voltage and different gate voltages in polycrystalline silicon thin-film transistors produces marked modifications both in the off current as well as device transconductance. These effects are explained in terms of hot-carrier effects related to a combination of charge injection into the gate insulator and formation of interface states near the drain.