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首页> 外文期刊>IEE proceedings. Part G >1.1 V full-swing double bootstrapped BiCMOS logic gates
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1.1 V full-swing double bootstrapped BiCMOS logic gates

机译:1.1 V全摆幅双自举BiCMOS逻辑门

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摘要

A new generation of noncomplementary BiCMOS digital gates for low-voltage, low-power applications is presented. These include an inverter and a NAND gate. A bootstrapping technique is employed in the pull-up and pull-down cycles to give high speed and a rail-to-rail operation. The performance evaluation has shown that the new circuits outperform the CMOS and the recently reported circuits in terms of speed, output voltage swing, power-delay product and maximum operating frequency. The crossover capacitance of the new circuit has been shown to be 50 per cent lower than the B/sup 2/CMOS. A transient model for the basic circuit configuration is developed to relate the key device parameters to the pull-up response, and HSPICE simulations have been used to characterise the circuits. The experimental results have also verified the operation of the proposed circuit.
机译:提出了适用于低压,低功耗应用的新一代非互补BiCMOS数字门。这些包括反相器和与非门。在上拉和下拉周期中采用了自举技术,以实现高速和轨到轨操作。性能评估表明,新电路在速度,输出电压摆幅,功率延迟乘积和最大工作频率方面均胜过CMOS和最近报道的电路。新电路的交叉电容已显示出比B / sup 2 / CMOS低50%。开发了用于基本电路配置的瞬态模型,以将关键器件参数与上拉响应相关联,并且已使用HSPICE仿真来表征电路。实验结果也验证了所提出电路的操作。

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