Ultralow-power SRAM technology

摘要

An ultmlow-standby-power technology has been developed in both 0.18-μm and 0.13-μm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 μm~2 and 2.34 μm~2, corresponding respectively to the 0.18-μm and 0.13-μm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25℃ and is less than 400 fA per cell at 1.5 V, 85℃. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.