Hardware design and modeling of lightweight block ciphers for secure communications

摘要

Lightweight ciphers are essential for secure communication in resource-constrained devices. The objective of this research is to implement lightweight ciphers in hardware; and optimize and model their design metrics. Design metrics are measured by advanced design flow which includes implementing ciphers in hardware and conducting simulations. To achieve the stated objective, the presented study selects one representative cipher–namely the KATAN/KTANTAN algorithms–to be modeled, implemented and optimized on specific hardware technology; the Field Programmable Gate Array (FPGA) platform. Various designs are implemented to exercise numerous options e.g. block sizes, number of implemented rounds and key scheduling. Then, design metrics are measured and modeled.In general, results demonstrate that number of resources and measured power consumption exhibit similar, but not identical, profile against design options. Measured energy trends are more complex. Specifically, results show that employing variable key scheduling increases resources, power and energy by 30%, 42% and 58%, respectively. Further, increasing the block size by 50% increases resources and power by about 53% and 55% respectively, but reduces energy by an average of 10%. Doubling number of implemented rounds in hardware increases resources and power by an average of 43% and 38% respectively. Optimum energy per bit design is produced in the designs with small block size (i.e. 32-bit) in the cases when number of implemented rounds equals to 32 or 64 rounds. When the energy and area design requirements are to be balanced, the optimum design is the 16-round implementation. Furthermore, developed models are tested on HIGHT cipher and demonstrate good accuracy.