Buffer design and insertion for global interconnections in 0.1 μm technology

摘要

This paper examines high-speed interconnection design in 0.1 μm technology from a simulation and modelling perspective. It is shown that using Cu metallisation in combination with a low-e dielectric can reduce the minimum delay considerably, as compared to using Al metallisation with SiO_2 as the inter-metal dielectric. Consequently, the use of Cu and a low-E dielectric leads to substantial saving of the surface area for buffers that are necessary to incorporate in order to maintain the improved performance when scaling down the device dimensions. As regard to buffer design and insertion, it is a good choice to allow the size of the cascaded inverters in each buffer to increase successively, and simultaneously to Permit the size-ratio of two consecutive inverters to increase along the signal propagation direction in order to minimise power consumption and delay. Furthermore, in order to save the precious Si surface area, it is preferable not to drive an interconnection line at a speed unnecessarily higher than the specified speed. Therefore, in parallel with the search for better conductors and insulators as well as improved interconnection technologies, there is an urgent need to address the interconnection issue from the circuit design perspective.