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Investigation on Degradation of SiC MOSFET Under Accelerated Stress in a PFC Converter

机译:PFC转换器加速应力下SiC MOSFET降解的调查

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The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this article, we report the longterm degradation phenomenon of several types of SiC MOSFETs in an actual 2-kW power factor correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional dc power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in a PFC converter. Online monitoring results show that the ON-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in ON-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain-source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation, and C-V measurement indicate that the main degradation mechanism is hot holes accumulation within the gate oxide above the JFET region and channel region due to high electric field stress.
机译:SiC MOSFET的可靠性问题已被各种加速应力测试广泛调查。然而,这些常规测试主要在简化和受控的测试环境中进行,这可能或可能无法实际地模拟功率转换器中的实际设备操作配置文件。在本文中,我们在实际的2-kW功率因数校正(PFC)转换器中报告了几种类型的SiC MOSFET的Longterm降级现象,并提供了降解机制的分析。与传统的DC电力循环试验相比,由于PFC转换器中的SiC MOSFET的栅极氧化物降低,观察到阈值电压的大幅度降低。在线监测结果表明,SiC MOSFET的导通电压降随着应力时间的增加而连续上升。导通电压的增加是由封装电阻和沟道电阻的变化引起的。栅极氧化物劣化导致漏极源漏电流和栅极漏电流的大幅增加。同时,米勒平台电压和阈值电压的变化导致SiC MOSFET中的开启损耗发生了显着变化。 TCAD模拟和C-V测量表明,由于高电场应力,主劣化机构是JFET区域和沟道区上方的栅极氧化物内的热孔积聚。

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