Process Compensation Loops for High Speed Ring Oscillators in Sub-Micron CMOS

摘要

In this paper, we present two implementations of a closed-loop process compensation scheme for high speed ring oscillators—the comparator based and the switched capacitor based loops. We provide detailed discussion of the frequency accuracy, loop stability, and implementation cost for each design. More than 150 test chips from multiple wafer-runs in a 90 nm CMOS process verify that frequency accuracy of better than 2.6% can be achieved with the application of the proposed compensation loop. Moreover, by leveraging a low variation addition-based current source, we have demonstrated a fully-integrated 2.15 GHz ring oscillator with less than 4.6% frequency variation without external references or post fabrication calibration, which is 3.8 $times$ improvement in frequency accuracy over the baseline case. The same compensation scheme can also alleviate frequency drift caused by temperature.