A novel quadrature multi loop CMOS ring oscillator with current compensation technique

摘要

A novel quadrature multi-loop CMOS ring oscillator, employing a current compensation technique and offering a wide frequency tuning range, low power consumption and small silicon area, is proposed. A current mirror on the output terminal is used to reduce the mismatch between the source-follower and the latch inverter, and it also helps to shrink the dimensions of the source-follower in the phase-shift network. The oscillator was designed in a 1P6M SMIC 180nm CMOS standard logic process. The post simulation with layout parasitic parameters shows the oscillator's tuning range is 0.25GHz to 5.82GHz. Over the tuning range, the phase noise varies from -105dBc/Hz to -115dBc/Hz @10MHz offset. The maximum power consumption is 31mw from a 1.8V supply. The multi loop CMOS ring oscillator occupies a very small area of 37 μm × 44 μm.