Delay locked loop for sub-micron single-poly digital CMOS processes

摘要

A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal. A method of phase locking an output clock with a reference clock includes, checking the occurrence of an aliased condition, increasing the speed of the output clock in response to an aliased condition, and increasing the speed of the output clock if the output clock is lagging the reference clock and decreasing the speed of the output clock if the output clock is leading the reference clock.