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Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop

机译:扩展比较器,用于控制延迟锁定环或锁相环中的数字延迟线

摘要

A digital delay locked loop (DLL) includes a phase detector that measures the phase difference between a signal to be synchronized and a reference signal. The phase detector produces an increase or decrease signal in response to the phase difference between the two signals. This signal is received by a binary counter, which changes its count in response. The output of the binary counter is supplied to a comparator logic that implements a thermometer coding scheme. Each of the comparator output signals enables or disables a corresponding transistor stack in a delay line, thereby changing the delay of the signal propagating through the delay line.
机译:数字延迟锁定环(DLL)包括一个相位检测器,用于测量要同步的信号与参考信号之间的相位差。相位检测器响应于两个信号之间的相位差而产生增大或减小的信号。该信号由二进制计数器接收,该二进制计数器会相应地更改其计数。二进制计数器的输出提供给实现温度计编码方案的比较器逻辑。每个比较器输出信号启用或禁用延迟线中的相应晶体管堆栈,从而更改通过延迟线传播的信号的延迟。

著录项

  • 公开/公告号US7079615B2

    专利类型

  • 公开/公告日2006-07-18

    原文格式PDF

  • 申请/专利权人 DANIEL WILLIAM BAILEY;

    申请/专利号US20010988691

  • 发明设计人 DANIEL WILLIAM BAILEY;

    申请日2001-11-20

  • 分类号H03D3/24;

  • 国家 US

  • 入库时间 2022-08-21 21:44:01

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