Higher radix linear sequential circuit implementation via hybrid U and JK multiple-valued logic primitives

摘要

The implementation of a 2-digit modulo-3 linear sequential circuit (LSC) is presented, together with its associated state diagram. Two multiple valued logic (MVL) primitives are identified as suitable building blocks for the realisation of the three basic elements required for higher radix (<2) LSC hardware. Specifically, the hybrid MVL combinational U-gate and the MVL sequential JK flipflop sequencer are identified as vehicles for the implementation of modulo-radix scalars, adders and delayers.