All-digital multipoint adaptive delay compensation circuit for low skew clock distribution

摘要

The authors describe an all-digital circuit for automatically controlling skew in the distribution of a clock or data signal over a single line. The circuit derives a compensating delay for any location such that a signal applied at one end emerges at the same global time at all sites. This is an alternative to delay-equalised hierarchical trees for use in large ICs, computers, and digital switches. A 3 /spl mu/m CMOS prototype at eight sites spread over 16 m shows adaptive skew control to within +/- 1.5 primitive buffer delays of the process employed. A novel technique for accommodating metastability is involved in the design.