3d Stacked Ics Reach Demo Stage

摘要

IMEC, a leading independent research center in nano-electronics and nanotechnology, recently demonstrated the first functional 3D integrated circuits obtained by die-to-die stacking using 5-um copper through-silicon vias (TSV). The research institute, based in Leuven, Belgium, said it will now develop 3D SIC chips on 200- and 300-mm wafers, integrating test circuits from partners participating in its 3D integration research program. For stacking, the top die was thinned down to 25 um and bonded to the landing die by Cu-Cu ther-mocompression. The dies were realized on 200-mm wafers in IMEC's reference 0.13-um CMOS process with an added Cu-TSVs process. IMEC is up-scaling the process for die-to-wafer bonding and reports it is on track for migrating the process to its 300-mm platform. To evaluate the impact of the 3D SIC flow on the characteristics of the stacked layers, both the top and landing wafers contained CMOS circuits. According to IMEC, extensive tests confirmed that the performance of the circuits does not degrade with adding Cu TSVs and stacking. To test the integrity and performance of the 3D stack, ring oscillators with varying configurations were made, distributed over the two chip layers and connected with the Cu TSVs. Tested after the TSV and stacking process, these circuits demonstrated chip integrity.