Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications

摘要

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical $(hbox{n}^{+}/hbox{p}^{+})$ polysilicon gates. CMOS-compatible $V_{T}$''s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.