Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

摘要

We compared the electrical characteristics, including mobility and on -state current $I_{rm on}$, of $hbox{n}^{+}$-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights $H_{rm fin}$ . The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length $L_{g}$ decreases, $I_{rm on}$ for devices with tall fins becomes worse, probably due to a high parasitic resistance $R_{p}$. Furthermore, $V_{rm th}$ variation increased with increasing $H_{rm fin}$ due to rough etching of the fin sidewall. Process technologies for reducing $R_{p}$ and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.